High performance host queue monitor for PCIE SSD controller
US10089255B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jul 25, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Dec 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory systems may include a plurality of queues, a queue ready indicator suitable for grouping the plurality of queues into a predefined number of queue ranges, each queue range having associated with it a queue range ready signal, and setting a queue range ready signal to ready when each queue in the queue range associated with the queue range ready signal is ready for processing, and a queue process sequencer suitable for determining a queue range ready for processing based on the queue range ready signals, and processing a queue within the queue range determined to be ready for processing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.