Binary neural networks on progammable integrated circuits
US10089577B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 5, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Sep 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17732
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an example, a circuit of a neural network implemented in an integrated circuit (IC) includes a layer of hardware neurons, the layer including a plurality of inputs, a plurality of outputs, a plurality of weights, and a plurality of threshold values, each of the hardware neurons including: a logic circuit having inputs that receive first logic signals from at least a portion of the plurality of inputs and outputs that supply second logic signals corresponding to an exclusive NOR (XNOR) of the first logic signals and at least a portion of the plurality of weights; a counter circuit having inputs that receive the second logic signals and an output that supplies a count signal indicative of the number of the second logic signals having a predefined logic state; and a compare circuit having an input that receives the count signal and an output that supplies a logic signal having a logic state indicative of a comparison between the count signal and a threshold value of the plurality of threshold values; wherein the logic signal output by the compare circuit of each of the hardware neurons is provided as a respective one of the plurality of outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.