Memory test data generating circuit and method
US10090061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Jul 13, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory test data generating circuit and method for generating a plurality of sets of test data is provided. The plurality of sets of test data is provided to a memory via a plurality of channels by a memory controller and is for testing the memory. The memory test data generating circuit includes: a plurality of counters, generating a plurality of counter values; and a data repetition and combination unit, generating the plurality of sets of test data according to the plurality of counter values, a bit width between the memory test data generating circuit and the memory controller, and a bit width between the memory controller and the memory. The test data of each channel is an identical and periodical data series.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.