Integrated circuits with standard cell
US10090289B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 15, 2017 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Nov 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/974
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides an integrated circuit with a dummy standard cell. The integrated circuit includes: a first metal line and a second metal line stretching along a first direction; a first dummy gate and a second dummy gate stretching along a second direction; Plural fin structures stretching along the first direction; A gate structure disposed on the fin structures and stretching along the second direction; Plural sets of short contact plug and long contact plug disposed between the first dummy gate, the second dummy gate and the gate structures; a doping region overlaps with the long contact plugs; a gate contact plug disposed on the gate structures; plural contact plugs disposed on and electrical contact the long contact plugs; A metal layer includes the first metal line, the second metal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.