Semiconductor memory device

US10090312B2 · kind B2 · utility

Assignee

• TOSHIBA MEMORY CORPORATION · JP

Inventors

• Shingo Nakajima · Yokohama, JP
• Hiroyasu Tanaka · Atsugi, JP

Key dates

• Filing date: Aug 19, 2016
• Grant date: Oct 2, 2018
• Expiry date: Aug 19, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/683

Abstract

According to the embodiments, the semiconductor memory device includes a semiconductor substrate, a first conducting layer, a semiconductor layer, a plurality of second conducting layer, and an electric charge accumulating layer. The first conducting layer is disposed on the semiconductor substrate via an insulating layer. The semiconductor layer is disposed on the first conducting layer and extends in a first direction above the semiconductor substrate. The plurality of the second conducting layers extends in a second direction intersecting with the first direction, and is laminated along the first direction via an insulating layer, and is disposed on the first conducting layer. The electric charge accumulating layer is disposed between the semiconductor layer and the plurality of second conducting layer. The semiconductor substrate includes an n type semiconductor region facing an end portion of the semiconductor layer.