Semiconductor memory device in which an array chip including three-dimensionally disposed memory cells bonded to a control circuit chip
US10090315B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2016 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Dec 22, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06541
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.