Resistive memory devices
US10090462B2 · kind B2 · utility
1Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2015 |
| Grant date | Oct 2, 2018 |
| Priority date | — |
| Expiry date | Aug 5, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/55
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Electronic apparatus, systems, and methods can include a resistive memory cell having a structured as an operably variable resistance region between two electrodes and a metallic barrier disposed in a region between the dielectric and one of the two electrodes. The metallic barrier can have a structure and a material composition to provide oxygen diffusivity above a first threshold during program or erase operations of the resistive memory cell and oxygen diffusivity below a second threshold during a retention state of the resistive memory cell. Additional apparatus, systems, and methods are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.