Patent · US Active

Allowing deletion of a dispatched instruction from an instruction queue when sufficient processor resources are predicted for that instruction

US10095518B2 · kind B2 · utility

0Cited by

0References

18Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Andrew James Antony Lees · Cambridge, GB
Ian Michael Caulfield · Cambridge, GB
Peter Richard Greenhalgh · Cambridge, GB

Key dates

Filing date	Nov 16, 2015
Grant date	Oct 9, 2018
Priority date	—
Expiry date	Aug 17, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG06F9/3851
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Instruction queue circuitry maintains an instruction queue to store fetched instructions. Instruction decode circuitry decodes instructions dispatched from the queue. The instruction decode circuitry allocates processor resource(s) for use in execution of the decoded instruction. Detection circuitry detect, for an instruction to be dispatched from a given instruction queue, a prediction indicating whether sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry. Dispatch circuitry dispatches an instruction from the queue to the instruction decode circuitry and allows deletion of the dispatched instruction from that instruction queue when the prediction indicates that sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.