Methods and structures to prevent sidewall defects during selective epitaxy

US10096474B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Niloy Mukherjee · Beaverton, US
• Niti Goel · Portland, US
• Sanaz K. Gardner · Portland, US
• Pragyansri Pathi · Portland, US
• Matthew V. Metz · Portland, US
• Sansaptak Dasgupta · Hillsboro, US
• Seung Hoon Sung · Beaverton, US
• James M. Powers · Paradise Valley, US
• Gilbert Dewey · Beaverton, US
• Benjamin Chu-Kung · Portland, US
• Jack T. Kavalieros · Portland, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: May 24, 2017
• Grant date: Oct 9, 2018
• Expiry date: May 24, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/08
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.