Lane-striped computation of packet CRC to maintain burst error properties
US10097203B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2015 |
| Grant date | Oct 9, 2018 |
| Priority date | — |
| Expiry date | Feb 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A CRC generator, a method for computing a CRC of a data packet, and an electronic system, such as a circuit board, are disclosed herein. In one embodiment the method is for computing the CRC of a data packet to be transmitted on a serial communications link having multiple lanes. In one embodiment, the CRC generator includes: (1) a CRC calculator configured to define a CRC calculation of a data packet in sequential order and perform parallelized computations, according to the sequential order and the multiple lanes, to generate sub-CRC values and (2) combination circuitry configured to combine the sub-CRC values to provide the CRC value for the packet.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.