System and method for improving the graphics performance of hosted applications
US10099129B2 · kind B2 · utility
1Cited by
2References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 19, 2016 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Sep 19, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/6405
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
One or more hardware components identify a bottleneck stage within a processor pipeline that processes frames of a video stream. The bottleneck stage has a first clock. An upstream stage receives a feedback signal from the bottleneck stage. The upstream stage has a second clock and the feedback signal includes information as to time required by the bottleneck stage to operate on data and information as to time the data spent queued. The upstream stage adjusts the speed at which the upstream stage operates and queues data to approximate the speed at which the bottleneck stage is operating and queuing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.