Mitigating read errors following programming in a multi-level non-volatile memory
US10101931B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Jun 4, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Read errors following programming in a multi-level non-volatile memory are mitigated by a controller of the non-volatile memory. The controller temporarily buffers, in a cache, pages of data programmed into the non-volatile memory. In response to receiving a read request for a target page of data programmed into the non-volatile memory, where the read request is received during a delay time affecting the target page, the controller services the read request by accessing data of the target page in the cache in response to the read request hitting in the cache. The controller instead services the read request from the non-volatile memory in response to the read request missing in the cache. When servicing the read request from the non-volatile memory, the controller preferably reads the target page from the non-volatile memory utilizing a set of read voltage thresholds determined based on the read-after-write delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.