Hardware counters to track utilization in a multithreading computer system
US10102004B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2014 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Feb 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/5083
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments relate tracking utilization in a multithreading (MT) computer system. According to one aspect, a computer system includes a configuration with a core configured to operate in a MT that supports multiple threads on shared resources of the core. The core is configured to perform a method that includes resetting a plurality of utilization counters. The utilization counters include a plurality of sets of counters. During each clock cycle on the core, a set of counters is selected from the plurality of sets of counters. The selecting is based on a number of currently active threads on the core. In addition, during each clock cycle a counter in the selected set of counters is incremented based on an aggregation of one or more execution events at the multiple threads of the core. Values of the utilization counters are provided to a software program.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.