Instruction and logic for run-time evaluation of multiple prefetchers

US10102134B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Zeshan A. Chishti · Hillsboro, US
• Christopher B. Wilkerson · Portland, US
• Seth H. Pugsley · Hillsboro, US
• Peng-Fei Chuang · Redwood City, US
• Robert L. Scott · Gilbert, US
• Aamer Jaleel · Northborough, US
• Shih-Lien Linus Lu · Hsinchu, TW
• Kingsum Chow · Portland, US

Key dates

• Filing date: Jun 23, 2016
• Grant date: Oct 16, 2018
• Expiry date: Aug 18, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/6026
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processor includes a cache, a prefetcher module to select information according to a prefetcher algorithm, and a prefetcher algorithm selection module. The prefetcher algorithm selection module includes logic to select a candidate prefetcher algorithm determine and store memory addresses of predicted memory accesses of the candidate prefetcher algorithm when performed by the prefetcher module, determine cache lines accessed during memory operations, and evaluate whether the determined cache lines match the stored memory addresses. The prefetcher algorithm selection module further includes logic to adjust an accuracy ratio of the candidate prefetcher algorithm, compare the accuracy ratio with a threshold accuracy ratio, and determine whether to apply the first candidate prefetcher algorithm to the prefetcher module.