Inventor · Northborough, MA, US

Aamer Jaleel

24Patents
6h-index
75Co-inventors
68Inventor score

Filing activity: Mar 21, 2007 → Oct 11, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7725657B2 Dynamic quality of service (QoS) for a shared cache Physics 26 Active
US10331583B2 Executing distributed memory operations using processing elements connected by distributed channels Physics 23 Active
US9720730B2 Providing an asymmetric multicore processor system transparently to an operating system Emerging Cross-Sectional Technologies 12 Active
US8407421B2 Cache spill management techniques using cache spill prediction Physics 11 Active
US8347301B2 Device, system, and method of scheduling tasks of a multithreaded application Emerging Cross-Sectional Technologies 10 Active
US8533422B2 Instruction prefetching using cache line history Emerging Cross-Sectional Technologies 9 Active
US10387319B2 Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support features Emerging Cross-Sectional Technologies 5 Active
US8769201B2 Technique for controlling computing resources Emerging Cross-Sectional Technologies 5 Active
US8132172B2 Thread scheduling on multiprocessor systems Physics 5 Active
US9262327B2 Signature based hit-predicting cache Physics 4 Active
US9378021B2 Instruction and logic for run-time evaluation of multiple prefetchers Physics 3 Active
US10102134B2 Instruction and logic for run-time evaluation of multiple prefetchers Physics 3 Active
US9792212B2 Virtual shared cache mechanism in a processing device Physics 2 Active
US10853276B2 Executing distributed memory operations using processing elements connected by distributed channels Physics 1 Active
US8839259B2 Thread scheduling on multiprocessor systems Physics 1 Active
US10284470B2 Technologies for network device flow lookup management Electricity 0 Active
US12321230B2 Alias-free tagged error correcting codes for machine memory operations Physics 0 Active
US11836361B2 Implementing compiler-based memory safety for a graphic processing unit Physics 0 Active
US12135781B2 Implementing hardware-based memory safety for a graphic processing unit Physics 0 Active
US11513957B2 Processor and method implementing a cacheline demote machine instruction Emerging Cross-Sectional Technologies 0 Active
US9710380B2 Managing shared cache by multi-core processor Emerging Cross-Sectional Technologies 0 Active
US8769209B2 Method and apparatus for achieving non-inclusive cache performance with inclusive caches Physics 0 Active
US9286128B2 Processor scheduling with thread performance estimation on cores of different types Physics 0 Active
US10817425B2 Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloads Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.