Patent · US Active

Method and apparatus for validating a test pattern

US10102329B2 · kind B2 · utility

0Cited by

0References

19Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Yoav Miller · Rehovot, IL
Asher Berkovitz · Kiryat Ono, IL
Sergey Sofer · Rishon LeZion, IL

Key dates

Filing date	Dec 13, 2013
Grant date	Oct 16, 2018
Priority date	—
Expiry date	May 25, 2034

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/333
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A method and apparatus of validating a test pattern for at-speed testing of at least one integrated circuit, IC, design. The method comprises calculating at least one weighted rise activity, WRA, value for at least one region of the IC design based at least partly on rising gate transitions within the at least one region of the IC design when the test pattern is applied thereto, calculating at least one weighted fall activity, WFA, value for the at least one region of the IC design based at least partly on fall gate transitions within the at least one region of the IC design when the test pattern is applied thereto, and validating the test pattern based at least partly on the WRA value and the WFA value.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.