Asher Berkovitz
14Patents
2h-index
17Co-inventors
40Inventor score
Filing activity: Mar 28, 2011 → May 28, 2014
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9709629B2 | Method and control device for launch-off-shift at-speed scan testing | Physics | 3 | Active |
| US9836567B2 | Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuit | Emerging Cross-Sectional Technologies | 2 | Active |
| US9141753B2 | Method for placing operational cells in a semiconductor device | Emerging Cross-Sectional Technologies | 2 | Active |
| US9171117B2 | Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program product | Physics | 2 | Active |
| US10746795B2 | Method and apparatus for at-speed scan shift frequency test optimization | Physics | 2 | Active |
| US9038006B2 | Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysis | Physics | 1 | Active |
| US9235673B2 | Apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage medium | Physics | 1 | Active |
| US9542523B2 | Method and apparatus for selecting data path elements for cloning | Physics | 1 | Active |
| US10102329B2 | Method and apparatus for validating a test pattern | Physics | 0 | Active |
| US9903916B2 | Scan test system with a test interface having a clock control unit for stretching a power shift cycle | Physics | 0 | Active |
| US9792399B2 | Integrated circuit hierarchical design tool apparatus and method of hierarchically designing an integrated circuit | Physics | 0 | Active |
| US9607117B2 | Method and apparatus for calculating delay timing values for an integrated circuit design | Physics | 0 | Active |
| US9652572B2 | Method and apparatus for performing logic synthesis | Physics | 0 | Active |
| US9977849B2 | Method and apparatus for calculating delay timing values for an integrated circuit design | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.