Non-volatile semiconductor storage device for reducing the number of memory cells arranged along a control to which a memory gate voltage is applied
US10102911B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2015 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Dec 11, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device in which, while voltage from a first control line is applied, as a memory gate voltage, to a sub control line through a switching transistor, another switching transistor can block voltage application to a corresponding sub control line. Thus, while a plurality of memory cells are arranged in one direction along the first control line, the number of memory cells to which a memory gate voltage is applied can reduced by the switching transistor, which reduces the occurrence of disturbance, accordingly. The sub control line to which the memory gate voltage is applied from the first control line is used as the gates of memory transistors, and thus the sub control line and the gates are disposed in a single wiring layer, thereby achieving downsizing as compared to a case in which the sub control line and the gates are disposed in separate wiring layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.