Memory device
US10103165B2 · kind B2 · utility
8Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Apr 7, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of vertical holes extending in a direction perpendicular to the upper surface of the substrate to penetrate through the gate structure, and a plurality of vertical structures in the plurality of vertical holes, respectively, each vertical structure of the plurality of vertical structures including an embedded insulating layer, and a plurality of channel layers separated from each other, the plurality of channel layers being outside the embedded insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.