Error correcting analog-to-digital converters
US10103753B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2017 |
| Grant date | Oct 16, 2018 |
| Priority date | — |
| Expiry date | Dec 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/164
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pipeline ADC comprising an ADC segment and a digital backend coupled to the ADC segment. In some examples the ADC is configured to receive an analog signal, generate a first partial digital code representing a first sample of the analog signal, and generate a second partial digital code representing a second sample of the analog signal. In some examples the digital backend is configured to receive the first and second partial digital codes from the ADC segment, generate a combined digital code based at least partially on the first and second partial digital codes, determine a gain error of the ADC segment based at least partially on a first correlation of a PRBS with a difference between the first and second partial digital codes, and apply a first correction to the combined digital code based at least partially on the gain error of the ADC segment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.