Viswanathan Nagarajan
15Patents
4h-index
31Co-inventors
56Inventor score
Filing activity: Jul 14, 2009 → May 31, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7961123B2 | Time-interleaved analog-to-digital converter | Electricity | 18 | Active |
| US7898446B2 | Correction of sampling mismatch in time-interleaved analog-to-digital converters | Electricity | 8 | Active |
| US10103753B1 | Error correcting analog-to-digital converters | Electricity | 7 | Active |
| US9748966B2 | Histogram based error estimation and correction | Electricity | 6 | Active |
| US10320405B2 | Pattern based estimation of errors in ADC | Electricity | 1 | Active |
| US10541700B2 | Gain and memory error estimation in a pipeline analog to digital converter | Electricity | 1 | Active |
| US8390488B2 | Non-linearity correction that is independent of input common mode, temperature variation, and process variation | Electricity | 1 | Active |
| US10581406B2 | Digital filtering for analog gain/phase errors | Electricity | 1 | Active |
| US11309902B2 | Gain and memory error estimation in a pipeline analog to digital converter | Electricity | 0 | Active |
| US10419036B2 | Error correcting analog-to-digital converters | Electricity | 0 | Active |
| US11962318B2 | Calibration scheme for a non-linear ADC | Electricity | 0 | Active |
| US9941893B2 | Pattern based estimation of errors in ADC | Electricity | 0 | Active |
| US11955984B2 | Analog-to-digital converter (ADC) having selective comparator offset error tracking and related corrections | Electricity | 0 | Active |
| US12074607B2 | Analog-to-digital converter (ADC) having linearization circuit with reconfigurable lookup table (LUT) memory and calibration options | Electricity | 0 | Active |
| US11881867B2 | Calibration scheme for filling lookup table in an ADC | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.