Processors and methods for cache sparing stores
US10108548B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2015 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Sep 8, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one aspect, a processor has a register file, a private Level 1 (L1) cache, and an interface to a shared memory hierarchy (e.g., an Level 2 (L2) cache and so on). The processor has a Load Store Unit (LSU) that handles decoded load and store instructions. The processor may support out of order and multi-threaded execution. As store instructions arrive at the LSU for processing, the LSU determines whether a counter, from a set of counters, is allocated to a cache line affected by each store. If not, the LSU allocates a counter. If so, then the LSU updates the counter. Also, in response to a store instruction, affecting a cache line neighboring a cache line that has a counter that meets a criteria, the LSU characterizes that store instruction as one to be effected without obtaining ownership of the effected cache line, and provides that store to be serviced by an element of the shared memory hierarchy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.