MIPS Tech, LLC
51Patents
50Active
51Granted
50Portfolio score
Filing activity: Nov 21, 2005 → Apr 30, 2024 · 3 expiring within 5 years
Most-cited patents
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7386701B2 | Prefetching hints | Physics | 17 | Expired |
| US10642501B1 | Hardware virtualized input output memory management unit | Physics | 14 | Active |
| US7509480B2 | Selection of ISA decoding mode for plural instruction sets based upon instruction address | Physics | 10 | Active |
| US8171262B2 | Method and apparatus for clearing hazards using jump instructions | Physics | 9 | Active |
| US10318304B2 | Conditional branch prediction using a long history | Physics | 3 | Active |
| US9870225B2 | Processor with virtualized instruction set architecture and methods | Physics | 3 | Active |
| US9940168B2 | Resource sharing using process delay | Physics | 3 | Active |
| US10846089B2 | Unified logic for aliased processor instructions | Physics | 2 | Active |
| US10423417B2 | Fault tolerant processor for real-time systems | Physics | 2 | Active |
| US11599270B2 | Virtualized-in-hardware input output memory management | Physics | 2 | Active |
| US10379861B2 | Decoding instructions that are modified by one or more other instructions | Physics | 2 | Active |
| US10108548B2 | Processors and methods for cache sparing stores | Physics | 1 | Active |
| US10649773B2 | Processors supporting atomic writes to multiword memory locations and methods | Physics | 1 | Active |
| US10459725B2 | Execution of load instructions in a processor | Physics | 1 | Active |
| US10534614B2 | Rescheduling threads using different cores in a multithreaded microprocessor having a shared register pool | Physics | 1 | Active |
| US10261798B2 | Indirect branch prediction | Physics | 1 | Active |
| US10754778B2 | Control of pre-fetch traffic | Physics | 1 | Active |
| US10318172B2 | Cache operation in a multi-threaded processor | Emerging Cross-Sectional Technologies | 1 | Active |
| US11829764B2 | Address manipulation using indices and tags | Physics | 1 | Active |
| US11080062B2 | Address manipulation using indices and tags | Physics | 1 | Active |
| US10025527B2 | Check pointing a shift register using a circular buffer | Physics | 1 | Active |
| US10782977B2 | Fault detecting and fault tolerant multi-threaded processors | Physics | 1 | Active |
| US12210876B2 | Implicit global pointer relative addressing for global memory access | Physics | 0 | Active |
| US12265475B2 | Translating virtual memory addresses to physical memory addresses | Physics | 0 | Active |
| US11635963B2 | Address manipulation using indices and tags | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.