Updating persistent data in persistent memory-based storage
US10108556B2 · kind B2 · utility
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5References
22Claims
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Key dates
| Filing date | Aug 25, 2016 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Sep 22, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a near memory cache, wherein the near memory cache comprises a cache line comprising an identifier associated with the transaction and a status flag indicating whether the cache line is committed or uncommitted, and a cache controller operatively coupled to the near memory cache to determine, based on the status flag, what operation is to be performed with respect to contents of the cache line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.