Partitioning circuit designs for implementation within multi-die integrated circuits
US10108773B1 · kind B1 · utility
2Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2016 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Mar 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Partitioning a circuit design can include determining, using a processor, a target area utilization and a target cut utilization by iterating over a range of timing violations and determining, using the processor, a worst allowed timing violation based upon the target area utilization and the target cut utilization. Circuit elements of the circuit design can be assigned to partitions, using the processor, for implementation of the circuit design in a multi-die integrated circuit based upon a partition cost calculated using the target area utilization, the target cut utilization, and the worst allowed timing violation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.