Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods
US10109342B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 11, 2017 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | May 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.