Patent assignee · US · COMPANY

ATOMERA INCORPORATED

106Patents
105Active
106Granted
61Portfolio score

Filing activity: Nov 21, 2014 → Jul 2, 2024

Most-cited patents

PatentTitleAreaCited byStatus
US9558939B1 Methods for making a semiconductor device including atomic layer structures using N2O as an oxygen source Electricity 98 Active
US9406753B2 Semiconductor devices including superlattice depletion layer stack and related methods Electricity 98 Active
US9899479B2 Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods Electricity 83 Active
US10084045B2 Semiconductor device including a superlattice and replacement metal gate structure and related methods Electricity 68 Active
US10109342B2 Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods Physics 67 Active
US10107854B2 Semiconductor device including threshold voltage measurement circuitry Electricity 65 Active
US10109479B1 Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice Electricity 65 Active
US9941359B2 Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods Electricity 65 Active
US9972685B2 Vertical semiconductor devices including superlattice punch through stop layer and related methods Electricity 59 Active
US10170603B2 Semiconductor device including a resonant tunneling diode structure with electron mean free path control layers Electricity 57 Active
US10191105B2 Method for making a semiconductor device including threshold voltage measurement circuitry Electricity 57 Active
US10170560B2 Semiconductor devices with enhanced deterministic doping and related methods Electricity 56 Active
US10170604B2 Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layers Electricity 56 Active
US10276625B1 CMOS image sensor including superlattice to enhance infrared light absorption Electricity 49 Active
US10249745B2 Method for making a semiconductor device including a resonant tunneling diode structure having a superlattice Electricity 48 Active
US10304881B1 CMOS image sensor with buried superlattice layer to reduce crosstalk Electricity 48 Active
US10593761B1 Method for making a semiconductor device having reduced contact resistance Electricity 44 Active
US10367028B2 CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice Electricity 43 Active
US10580866B1 Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance Electricity 42 Active
US10566191B1 Semiconductor device including superlattice structures with reduced defect densities Electricity 42 Active
US10468245B2 Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice Electricity 41 Active
US10608043B2 Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice Electricity 41 Active
US10461118B2 Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk Electricity 40 Active
US10580867B1 FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance Electricity 40 Active
US10381242B2 Method for making a semiconductor device including a superlattice as a gettering layer Electricity 40 Active

Source: USPTO / EPO open patent data. Counts and citation impact are objective bibliographic measures.