Etch profile control during skip via formation

US10109526B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Xunyuan Zhang · Albany, US
• Nicholas V. LiCausi · Watervliet, US
• J. Jay McMahon · Clifton Park, US
• Ryan Smith · San Clemente, US
• Errol Todd Ryan · Wappingers Falls, US
• Shao Beng Law · Watervliet, US

Key dates

• Filing date: May 31, 2017
• Grant date: Oct 23, 2018
• Expiry date: May 31, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76834
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.