Integrated circuit heat dissipation using nanostructures
US10109553B2 · kind B2 · utility
3Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2017 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Mar 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.