Wafer level chip scale semiconductor package
US10109564B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2017 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Feb 13, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/386
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.