Leo van Gemert
12Patents
2h-index
24Co-inventors
50Inventor score
Filing activity: Dec 29, 2009 → Dec 12, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10615134B2 | Integrated circuit package | Electricity | 3 | Active |
| US8679963B2 | Fan-out chip scale package | Electricity | 2 | Active |
| US10109564B2 | Wafer level chip scale semiconductor package | Electricity | 1 | Active |
| US10825789B1 | Underbump metallization dimension variation with improved reliability | Electricity | 1 | Active |
| US11963291B2 | Efficient wave guide transition between package and PCB using solder wall | Electricity | 0 | Active |
| US11557491B2 | Selective underfill assembly and method therefor | Electricity | 0 | Active |
| US10613136B2 | Apparatus comprising a semiconductor arrangement | Electricity | 0 | Active |
| US10315821B2 | Component carrier | Electricity | 0 | Active |
| US8482136B2 | Fan-out chip scale package | Electricity | 0 | Active |
| US12183595B2 | Selective underfill assembly and method therefor | Electricity | 0 | Active |
| US11011446B2 | Semiconductor device and method of making a semiconductor device | Electricity | 0 | Active |
| US11508669B2 | Method and apparatus for improved circuit structure thermal reliability on printed circuit board materials | Emerging Cross-Sectional Technologies | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.