Method for creating alternate hardmask cap interconnect structure with increased overlay margin

US10109583B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Robert L. Bristol · Portland, US
• Manish Chandhok · Beaverton, US
• Jasmeet S. Chawla · Hillsboro, US
• Florian Gstrein · Portland, US
• Eungnak Han · Portland, US
• Rami Hourani · Santa Clara, US
• Kevin Lin · Beaverton, US
• Richard E. Schenker · Portland, US
• Todd R. Younkin · Montgomery, US

Key dates

• Filing date: Dec 24, 2014
• Grant date: Oct 23, 2018
• Expiry date: Dec 24, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2221/1026
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.