Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength

US10109646B1 · kind B1 · utility

Assignee

• QUALCOMM Incorporated · US

Inventor

• Mustafa Badaroglu · Kessel-Lo, BE

Key dates

• Filing date: Jun 5, 2017
• Grant date: Oct 23, 2018
• Expiry date: Jun 5, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/924

Abstract

Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength is disclosed. The ability to vary the exposures of channel structures in 3D transistors from trench isolation allows the drive strengths of the 3D transistors to be varied. Varying the drive strengths of 3D transistors may be advantageous in certain circuit applications to reduce power consumption and/or control drive strength ratios between transistors, as examples. In this regard, in exemplary aspects disclosed herein, during the fabrication of 3D transistors, a trench isolation material is disposed adjacent to channel structures formed from a substrate. The amount of trench isolation material disposed adjacent to each channel structure determines the amount of channel structure surface area exposed to a gate. The amount of channel structure surface area of the 3D transistor exposed to the gate affects the drive strength of the 3D transistor.