Inventor · Kessel-Lo, BE

Mustafa Badaroglu

34Patents
7h-index
30Co-inventors
69Inventor score

Filing activity: Mar 16, 2001 → Jul 29, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US6941258B2 Method, apparatus and computer program product for determination of noise in mixed signal systems Physics 220 Expired
US8134358B2 Method of auto calibrating a magnetic field sensor for drift and structure therefor Physics 72 Active
US10332881B1 Integrating a gate-all-around (GAA) field-effect transistor(s) (FET(S)) and a finFET(s) on a common substrate of a semiconductor die Electricity 31 Active
US9871121B2 Semiconductor device having a gap defined therein Electricity 22 Active
US9793164B2 Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices Electricity 18 Active
US9799560B2 Self-aligned structure Electricity 13 Active
US10109646B1 Selectively recessing trench isolation in three-dimensional (3D) transistors to vary channel structure exposures from trench isolation to control drive strength Electricity 11 Active
US7987382B2 Method and apparatus for minimizing the influence of a digital sub-circuit on at least partially digital circuits Physics 7 Active
US8773157B2 Test circuit for testing through-silicon-vias in 3D integrated circuits Electricity 7 Active
US9953979B2 Contact wrap around structure Electricity 7 Active
US9824936B2 Adjacent device isolation Electricity 5 Active
US10283526B2 Standard cell circuits employing voltage rails electrically coupled to metal shunts for reducing or avoiding increases in voltage drop Electricity 4 Active
US9502414B2 Adjacent device isolation Electricity 4 Active
US10607896B2 Method of forming gate of semiconductor device and semiconductor device having same Electricity 4 Active
US10043796B2 Vertically stacked nanowire field effect transistors Electricity 3 Active
US9985014B2 Minimum track standard cell circuits for reduced area Electricity 3 Active
US9728718B2 Magnetic tunnel junction (MTJ) device array Electricity 3 Active
US10090244B2 Standard cell circuits employing high aspect ratio voltage rails for reduced resistance Electricity 2 Active
US10157992B2 Nanowire device with reduced parasitics Electricity 2 Active
US9570509B2 Magnetic tunnel junction (MTJ) device array Electricity 1 Active
US10079293B2 Semiconductor device having a gap defined therein Electricity 1 Active
US7885326B2 Method for determining a pulse position in a signal Electricity 1 Active
US8233579B2 Devices comprising delay line for applying variable delay to clock signal Electricity 1 Active
US10032678B2 Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices Electricity 1 Active
US12340304B2 Partial sum management and reconfigurable systolic flow architectures for in-memory computation Emerging Cross-Sectional Technologies 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.