Semiconductor metallization structure
US10109674B2 · kind B2 · utility
2Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2015 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Aug 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabrication of a device includes forming a first metallization layer that is coupled to a logic device of the device. The method further includes forming a second metallization layer that is coupled to a magnetoresistive random access memory (MRAM) module of the device. The second metallization layer is independent of the first metallization layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.