Efficient system debug infrastructure for tiled architecture
US10110234B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 19, 2017 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Jul 19, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/396
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods and apparatus are described for providing and operating an efficient infrastructure to implement a built-in clock stop and scan dump (CSSD) scheme for fabric blocks, such as block random access memory (BRAM), UltraRAM (URAM), digital signal processing (DSP) blocks, configurable logic elements (CLEs), and the like. This is a very useful feature for system debug and can also be applied for emulation use cases (e.g., FPGA emulation). This scheme can be applied to any tiled architecture that has highly repetitive blocks. The infrastructure may include a DFx controller shared across multiple tiled blocks with some distributed logic in each block, in an effort to minimize or at least reduce area overhead. The infrastructure may also minimize or at least reduce utilization of fabric resources in an effort to ensure the least perturbation of the original design, such that the design issues being debugged can be easily reproduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.