DLL circuit having variable clock divider
US10110240B1 · kind B1 · utility
9Cited by
1References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 17, 2017 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Oct 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0997
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein is an apparatus that includes a variable clock divider configured to divide a first clock signal to generate a second clock signal, a delay circuit configured to delay the second clock signal to generate a third clock signal, and a phase detector configured to compare phases of the second and third clock signals. The variable clock divider has a division ratio that is variable based, at least in part, on a delay amount of the delay circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.