Dual-photodiode image pixel
US10110839B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2016 |
| Grant date | Oct 23, 2018 |
| Priority date | — |
| Expiry date | Jul 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/133
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image sensor may have an array of pixels that include nested sub-pixels that each have at least one respective photodiode. An inner sub-pixel of a pixel with nested sub-pixels may have a relatively lower effective light collecting area compared to an outer sub-pixel of the pixel within which the inner sub-pixel is nested. A pixel circuit for the nested sub-pixels may include an overflow capacitor and/or a coupled gate circuit used to route charges from the photodiode in the inner sub-pixel. The lower light collecting area of the photodiode in the inner sub-pixel, with optional flicker mitigation charge routing from the coupled gates structure, may reduce the size of the capacitors required to capture photodiode and photodiode overflow charge responses. Flicker mitigation charge routing using a coupled gates structure may allow an adjustable proportion of the overflow charge to be stored in one or more storage capacitors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.