Method for controlling semiconductor deposition operation
US10113228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2014 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Apr 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2855
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
The present disclosure provides a method for controlling a semiconductor deposition operation. The method includes (i) identifying a first target lifetime in a physical vapor deposition (PVD) system; (ii) inputting the first target lifetime into a processor; (iii) outputting, by the processor, a plurality of first operation parameters according to a plurality of compensation curves; and (iv) performing the first operation parameters in the PVD system. The first operation parameters includes, but not limited to, an RF power tuning, a DC voltage tuning, a target to chamber pedestal spacing tuning, an AC bias tuning, an impedance tuning, a reactive gas flow tuning, an inert gas flow tuning, a chamber pedestal temperature tuning, or a combination thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.