Command control for multi-core non-volatile memory
US10114589B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Jan 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, and methods are disclosed for controlling commands for non-volatile memory. An apparatus includes one or more memory die. A memory die includes a command/address buffer, an on-die controller, and a plurality of non-volatile memory cores that share a data path. A core includes an array of non-volatile memory cells. A command/address buffer queues command and address information for a plurality of storage operations for one or more non-volatile memory cores. An on-die controller initiates a first unexecuted read operation and a first unexecuted write operation from a command/address buffer in parallel, in response to determining that core dependencies are satisfied for a read operation and a write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.