System and method for error detection of executed program code employing compressed instruction signatures

US10114685B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Steffen Sonnekalb · Munich, DE
• Andreas Wenzel · Munich, DE

Key dates

• Filing date: Feb 3, 2016
• Grant date: Oct 30, 2018
• Expiry date: Jun 15, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/452
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system comprising a first processor and a second processor is provided. The first processor is configured to load an instruction block from a first memory, wherein said instruction block comprises a plurality of opcodes and a stored error code. For each opcode of the plurality of opcodes of the instruction block, the first processor is configured to determine a first determined signature depending on said opcode. The first processor is configured to determine a determined error code for the instruction block depending on each opcode and depending on the first determined signature of each opcode of the plurality of opcodes of the instruction block. Moreover, the first processor is configured to determine that a first error occurred, if the determined error code is different from the stored error code. The second processor is configured to determine a second determined signature for a current opcode of the plurality of opcodes of the instruction block depending on said current opcode. Moreover, the second processor is configured to determine that a second error occurred, if the second determined signature for the current opcode is different from the first determined signature for t…