Memory erase management
US10114743B2 · kind B2 · utility
6Cited by
0References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2016 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Oct 7, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2957
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.