Data bit inversion tracking in cache memory to reduce data bits written for write operations
US10115444B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Aug 9, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Data bit inversion tracking in cache memory to reduce data bits written for write operations is disclosed. In one aspect, a cache memory including a cache controller and a cache array is provided. The cache array includes one or more cache entries, each of which includes a cache data field and a bit change track field. The cache controller compares a current cache data word to a new data word to be written and stores a bit track change word representing the difference (i.e., inverted bits) between the current cache data word and the new data word in the bit change track field. By using the bit track change word stored in the bit change track field to determine whether fewer bit writes are required to write data in an inverted or a non-inverted form, power consumption can be reduced for write operations through reduced bit write operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.