Hyunsuk Shin
37Patents
5h-index
39Co-inventors
65Inventor score
Filing activity: Sep 17, 2008 → Mar 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8185713B2 | Flexible sequencer design architecture for solid state memory controller | Physics | 18 | Active |
| US10558393B2 | Controller hardware automation for host-aware performance booster | Physics | 10 | Active |
| US8255615B1 | Flexible sequence design architecture for solid state memory controller | Physics | 8 | Active |
| US9152553B1 | Generic command descriptor for controlling memory devices | Physics | 8 | Active |
| US9146824B1 | Management of bit line errors based on a stored set of data | Physics | 7 | Active |
| US9552318B2 | Removable memory card type detection systems and methods | Physics | 5 | Active |
| US10613756B2 | Hardware-accelerated storage compression | Physics | 5 | Active |
| US9575884B2 | System and method for high performance and low cost flash translation layer | Physics | 5 | Active |
| US10185515B2 | Unified memory controller for heterogeneous memory on a multi-chip package | Physics | 4 | Active |
| US9401226B1 | MRAM initialization devices and methods | Physics | 4 | Active |
| US9633706B1 | Voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation | Physics | 4 | Active |
| US10115444B1 | Data bit inversion tracking in cache memory to reduce data bits written for write operations | Emerging Cross-Sectional Technologies | 4 | Active |
| US9081668B2 | Architecture to allow efficient storage of data on NAND flash memory | Emerging Cross-Sectional Technologies | 3 | Active |
| US8868852B2 | Interface management control systems and methods for non-volatile semiconductor memory | Physics | 3 | Active |
| US8626995B1 | Flexible sequence design architecture for solid state memory controller | Physics | 2 | Active |
| US8964498B2 | Systems and methods for reducing peak power consumption in a solid state drive controller | Physics | 2 | Active |
| US10360987B2 | Managing refresh for flash memory | Physics | 2 | Active |
| US10199115B2 | Managing refresh for flash memory | Physics | 2 | Active |
| US8788781B2 | Descriptor scheduler | Physics | 2 | Active |
| US11029856B2 | Flash memory device with data fragment function | Physics | 1 | Active |
| US10510382B2 | Hardware automated link control of daisy-chained storage device | Physics | 1 | Active |
| US9158675B2 | Architecture for storage of data on NAND flash memory | Emerging Cross-Sectional Technologies | 1 | Active |
| US9274888B2 | Method and apparatus for multiple-bit DRAM error recovery | Physics | 1 | Active |
| US10444999B2 | Universal flash storage (UFS) host design for supporting embedded UFS and UFS card | Physics | 1 | Active |
| US10725706B1 | Apparatus and method of scheduling universal flash storage refresh operations according to a refresh handover mechanism | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.