Spin transfer torque MRAM device with error buffer
US10115446B1 · kind B1 · utility
50Cited by
18References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2016 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Aug 3, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile error buffer is added to STT-MRAM memory design to reduce the error correction coding ECC required to achieve reliable operation with a non-zero Write Error Rate (“WER”). The error buffer is fully associative, storing both the address and the data of memory words which have failed to write correctly within an assigned ECC error budget. The write cycle includes a verify to determine if the word has been written correctly. The read cycle includes a search of the error buffer to determine if the address is present in the buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.