Frequency synthesis for memory input-output operations
US10115449B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Jan 25, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Jan 25, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory channel including an internal clock circuit is disclosed. The clock circuit may synthesize an internal clock signal for use by one or more components of the memory channel. The internal clock signal may have a different frequency than an external clock frequency. The memory channel may include multiple clock circuits that generate multiple internal clock signals. Each portion of the memory channel associated with a different clock circuit may be phase and/or frequency independent of the other portions of the memory channel. The clock circuit may synthesize an internal clock signal based on an external clock signal. The clock circuit may use encoded timing data from an encoded I/O scheme to align the phase of the internal clock signal to a data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.