Dean D. Gans
150Patents
13h-index
34Co-inventors
86Inventor score
Filing activity: Sep 18, 1996 → Mar 15, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6317381A | Method and system for adaptively adjusting control signal timing in a memory device | Physics | 120 | Expired |
| US6111812A | Method and apparatus for adjusting control signal timing in a memory device | Physics | 109 | Expired |
| US6304511A | Method and apparatus for adjusting control signal timing in a memory device | Physics | 83 | Expired |
| US6438043B2 | Adjustable I/O timing from externally applied voltage | Physics | 39 | Expired |
| US6130811A | Device and method for protecting an integrated circuit during an ESD event | Electricity | 26 | Expired |
| US5978311A | Memory with combined synchronous burst and bus efficient functionality | Physics | 21 | Expired |
| US6725316B1 | Method and apparatus for combining architectures with logic option | Physics | 19 | Expired |
| US9911469B1 | Apparatuses and methods for power efficient driver circuits | Physics | 19 | Active |
| US9766831B2 | Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination | Physics | 18 | Active |
| US5999466A | Method, apparatus and system for voltage screening of integrated circuits | Physics | 16 | Expired |
| US10715127B2 | Apparatuses and methods for using look-ahead duty cycle correction to determine duty cycle adjustment values while a semiconductor device remains in operation | Physics | 15 | Active |
| US6161204A | Method and apparatus for testing SRAM memory cells | Physics | 15 | Expired |
| US9935632B1 | Methods and systems for averaging impedance calibration | Physics | 14 | Active |
| US9601182B2 | Frequency synthesis for memory input-output operations | Physics | 13 | Active |
| US10164817B2 | Methods and apparatuses for signal translation in a buffered memory | Physics | 13 | Active |
| US10348270B2 | Apparatuses and methods for calibrating adjustable impedances of a semiconductor device | Electricity | 12 | Active |
| US5933378A | Integrated circuit having forced substrate test mode with improved substrate isolation | Physics | 11 | Expired |
| US6163500A | Memory with combined synchronous burst and bus efficient functionality | Physics | 11 | Expired |
| US9508409B2 | Apparatuses and methods for implementing masked write commands | Physics | 11 | Active |
| US11087819B2 | Methods for row hammer mitigation and memory devices and systems employing the same | Physics | 10 | Active |
| US10868519B2 | Apparatuses and methods for calibrating adjustable impedances of a semiconductor device | Electricity | 10 | Active |
| US6628139B2 | Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges | Electricity | 10 | Expired |
| US9934831B2 | Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters | Physics | 10 | Active |
| US10157647B2 | Apparatuses and methods for storing and writing multiple parameter codes for memory operating parameters | Physics | 9 | Active |
| US7489165B2 | Method and apparatus for amplifying a regulated differential signal to a higher voltage | Physics | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.