Compact three-dimensional memory device having a seal ring and methods of manufacturing the same
US10115681B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2018 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Mar 22, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/41
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die includes a pair of first alternating stacks of first portions of insulating layers and electrically conductive layers located over a semiconductor substrate, groups of memory stack structures vertically extending through a respective one of the pair of the first alternating stacks, a pair of second alternating stacks of second portions of the insulating layers and dielectric material layers laterally adjoined to a respective one of the first alternating stacks, such that each second portion of the insulating layers is connected to a respective one of the first portions of the insulating layers, and at least one seal ring structure laterally enclosing, and laterally spaced from, the pair of first alternating stacks, and contacting at least a first sidewall of each of the pair of second alternating stacks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.