Semiconductor package having a redistribution line structure
US10115708B2 · kind B2 · utility
3Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Mar 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package may include a first semiconductor chip having first bonding pads on a first active surface. The semiconductor package may include a second semiconductor chip having second bonding pads which are arranged on a second active surface. The first and second semiconductor chips are stacked such that the first and second active surfaces face each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.