Non-volatile memory devices and manufacturing methods thereof
US10115799B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2017 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | Jan 17, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/514
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.